A lateral diffusion metal-oxide-semiconductor field effect transistor (LDMOSFET) is a field effect transistor having a drift region between a gate and a drain region in order to avoid a high electric field at a drain junction, i.e., at the p-n junction between a body and the drain region. An LDMOSFET is typically employed in high voltage power applications involving voltages in the range from about 5 V to about 50 V, which is applied across the drain region and the source region. A substantial fraction of the high voltage may be consumed within the drift region in the LDMOSFET so that the electric field generated across the gate dielectric does not cause breakdown of the gate dielectric.
A thin gate dielectric is preferred on the source side of a gate electrode to apply a strong electric field to induce current flow, while a thick gate dielectric is preferred on the drain side of the gate electrode to prevent an excessive electric field across the gate oxide in the LDMOSFET. Methods of employing a thicker oxide on the drain side relative to the source side have been known in the art.
Referring to FIG. 1, an exemplary prior art LDMOSFET structure is shown, which comprises a substrate semiconductor region 110 containing a semiconductor material and having a doping of a first conductivity type and located in a semiconductor substrate 108. Typically, the dopant concentration of the substrate semiconductor region is low, i.e., from about 3.0×1014/cm3 to about 1.0×1016/cm3. A first conductivity type well 130 located in the semiconductor substrate 108 comprises the same semiconductor material as the substrate semiconductor region 110. The first conductivity type well 130 has a doping of the first conductivity type and has a dopant concentration higher than the doping concentration of the substrate semiconductor region 130. A LOCOS (local oxidation of silicon) oxide 150 is present on a portion of a top surface of the semiconductor substrate 108. The LOCOS oxide 150 has two bird's beaks and is integrally formed with a thin silicon oxide layer that is adjoined to one of the bird's beaks. A drift region 140 having a doping of a second conductivity type, which is the opposite of the first conductivity type, is located directly beneath a portion of the LOCOS oxide 150 within the semiconductor substrate 108. The drift region 140 comprises the same semiconductor material as the substrate semiconductor region 110.
A source region 142 and a drain region 144, each comprising a semiconductor material and having a doping of the second conductivity type, are located within the first conductivity type well 130 and the drift region 140, respectively. A substrate contact semiconductor region 132 comprising the semiconductor material and having a doping of the first conductivity type is also formed in the first conductivity type well 130 at a location farther away from the drift region 140 than the first conductivity type well 130. A source and substrate metal contact 182 is located on the source region 142 and the substrate contact semiconductor region 132. Likewise, a drain metal contact 184 is located on the drain region 184. A gate electrode 160 straddles a portion of the first conductivity type well 130 and the drift region 140. Optionally, a portion of the substrate semiconductor region 110 may abut a portion of the LOCOS oxide. A gate spacer 162 and a gate metal contact 186 are located on the gate electrode 160. LOCOS isolation 120 provides electrical isolation between various components on the surface of the semiconductor substrate 108.
Local oxidation of silicon (LOCOS) process employs a silicon substrate having a patterned oxygen-diffusion-resistant layer thereupon. Typically, the oxygen-diffusion-resistant layer is a silicon nitride layer. During a thermal oxidation process, exposed portions of the silicon substrate are thermally oxidized to form thermal silicon oxide. As oxygen atoms diffuse underneath the edge of the oxygen-diffusion-resistant layer, a tapered silicon oxide structure having a concave curvature known as a bird's beak is formed underneath the oxygen-diffusion-resistant layer. Formation of the bird's beak thus requires presence of the oxygen-diffusion-resistant layer. The LOCOS oxide 150 in the exemplary prior art semiconductor LDMOSFET structure is formed prior to formation of the gate electrode 160 by forming a patterned oxygen-diffusion-resistant layer, e.g., a silicon nitride layer, and performing a thermal oxidation of silicon.
For the LOCOS process, the gate electrode 160 is formed after the formation of the LOCOS oxide 150. Patterning of the gate electrode 160 is performed on a preexisting LOCOS oxide 150. The location of the bird's beak structure relative to the gate electrode 160 is subject to overlay variations of the alignment of the lithographic pattern of the gate electrode and the lithographic pattern of the oxygen-diffusion-resistant layer. Thus, it is inherent in the exemplary prior art LDMOSFET structure that the thickness profile of the LOCOS oxide 150, which is a gate oxide, is not self-aligned to an edge of the gate electrode 160, and as a consequence, performance of the exemplary prior art LDMOSFET has significant variations in terms of response of drain current as a function of a gate voltage.
The drain region 144 and the gate electrode 160 require separate lithographic steps for patterning. Thus, the drift distance L′ between the edge of the drift region underneath the gate electrode 160 and the proximal edge of the drain region 144 is subject to variation due to the lithographic overlay tolerance between the pattern for the drain region 144 and the pattern for the gate electrode 160. The variation in the overlay distance L′ introduces variation in the electrical resistance of the drift region 140. However, a high resistance of the drift region 140 is undesirable because current flow through the drift region 140 is impeded by such a high resistance.
Referring to FIG. 2, another prior art LDMOSFET structure disclosed by A. W. Ludikhuize, “High-Voltage DMOS and PMOS in Analog IC's,” IEDM 1982, pp. 81-84, comprises a gate dielectric 172 having multiple thicknesses. The body 132, which has a doping of a first conductivity type, laterally abuts the drift region 142, which has a doping of the second conductivity type, at an interface directly below the gate dielectric 172. The gate dielectric 172 has stepwise increases in thickness in the direction from an edge of a gate electrode 182 over the body 132 toward an edge of the gate electrode 182 over the drift region 142. A source region 152 and a drain region 162 are formed in distal ends of the body 132 and the drift region 142, respectively. The stepwise increase in the thickness of the gate dielectric 172 reduces electric field across the gate dielectric 172 near the edge of the gate electrode 182 over the drift region 142. The reduction in the electric field is beneficial to the integrity of the gate dielectric 172, especially in an off-state when a high voltage is applied across the portion of the gate dielectric 172 directly below the edge of the gate electrode 182 and over the drift region 142.
The portion of the gate electrode 182 which is over the drift region 142 is generally referred to as a “field plate.” While this example depicts the field plate as a portion of the gate electrode 182, it is sometimes formed as a distinct region which can be biased independently, but is generally biased at the same potential as the gate or source. In the case that the LDMOSFET is an n-type device, in an off-state, the gate electrode 182 and the source 152 are generally at approximately the same potential as the body 132, while the drain 162 is at a higher potential. An electric field exists laterally across the drift region 142, with the highest potential at the distal end near the drain 162, and the lowest magnitude potential at the proximal end near the body 132. An electric field also exists across the junction between drift region 142 and body 132. The electric field between gate electrode 182 and the drift region 142 causes an increased depletion of majority carriers in the drift region 142 below the gate electrode 182. This serves to reduce the electric field near the surface at the interface between the drift region 142 and the body 132, thereby increasing the effective breakdown voltage of the junction. For this reason, this type of device is termed “reduced surface field metal-oxide-semiconductor field effect transistor,” or RESURF MOSFET.
In the present example, when the device is on, the gate electrode 182 is generally at a higher potential than the source 152 and the body 132, while the potential of the drain 162 is often at approximately the same potential as the source 152 and the body 132. In this case, the resulting electric field between the gate electrode 182 and the drift region 142 causes an accumulation of majority carriers in the drift region 142, thus reducing the effective resistance of the drift region in the on-state, or “on-resistance.” As such, the addition of a field plate by extending the gate electrode over the drift region 142 provides a device which has an increased breakdown voltage between the body 132 and the drift region 142, yet has reduced on-resistance.
Here, the drift distance L′ is the distance between the edge of the drift region 142 underneath the gate electrode 182 and the proximal edge of the drain region 162. This drift distance L′ is also subject to variation due to the lithographic overlay tolerance between the pattern for the drain region 162 and the pattern for the gate electrode 182 since the gate electrode 182 and the drain region 162 are patterned in separate lithographic steps. The variation in the overlay distance L′ introduces variation in the electrical resistance of the drift region 142.
Typically, in order to minimize the electric field in the off-state of an LDMOSFET, the drift region is lightly doped and thus has a high resistance. However, the high resistance is undesirable in an on-state since the performance and efficiency is limited by the high resistance of the drift region. Reduction of on-resistance of the drift region generally comes at the expense of decreased breakdown voltage and device reliability, thus limiting the allowable operating voltage. Increase of resistance of the drift region results in an increase in the operating voltage at the expense of reduced performance and efficiency.
Thus, in order to provide a high performance and/or low power LDMOSFET, it is necessary to provide a tight control over the resistance of the drift region. Such tight control may be facilitated by a tight control over a drift distance, which is the distance between the edge of a drift region under an electrode and a proximal edge of a drain region.
In view of the above, there exists a need for an LDMOSFET structure providing a well controlled resistance for a drift region independent of overlay variations in lithographic steps of a manufacturing sequence, and methods of manufacturing the same.
Particularly, there exists a need for an LDMOSFET structure in which the drift distance is independent of overlay variations in lithographic steps of a manufacturing sequence, and methods of manufacturing the same.